| 摘要 |
A leadframe is provided to guarantee price competitiveness and mass production by reducing the thickness of a Pd+Co alloy plating layer by at least a half. A semiconductor chip is mounted on a chip pad. The semiconductor chip is connected to an external circuit by a plurality of inner leads and outer leads. A dam bar is formed in a boundary part of the inner lead and the outer lead. A lead lock is formed on the inner lead to fix the inner lead. In the chip pad, the inner lead, the outer lead and the dam bar, a Ni plating layer(22) of 0.2-2 mum, a Pd+Co alloy plating layer(23) of 0.05 mum and an Au plating layer(24) of 0.001-0.1 mum are sequentially stacked as a bottom metal coating on a base layer(21). In the Pd+Co alloy plating layer, the ratio of Pd to Co is 75:25-99:1. |
