发明名称 |
Digital registered data buffer for use in RAM memory system, has clock output of phase-locked loop providing clock signal shifted in phase by specific degree plus fraction of clock period with respect to feedback clock signal |
摘要 |
<p>The buffer has a clock output of a phase-locked loop providing a feedback clock signal for application to a feedback input of the loop. Another clock output provides a clock signal shifted in phase by a fraction of the clock period with respect to the feedback clock signal for application to a clock input (CLK) of a data register. A third clock output provides a clock signal shifted in phase by an amount of specific degree plus a fraction of the clock period with respect to the feedback clock signal for application to a clock input of a data destination device e.g. static dynamic RAM. An independent claim is also included for a memory system comprising a memory controller.</p> |
申请公布号 |
DE102006049310(A1) |
申请公布日期 |
2008.05.08 |
申请号 |
DE20061049310 |
申请日期 |
2006.10.19 |
申请人 |
TEXAS INSTRUMENTS DEUTSCHLAND GMBH |
发明人 |
NAUJOKAT, JOERN |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|