| 摘要 |
PROBLEM TO BE SOLVED: To provide a data transfer control device, in which a CPU accesses a memory on a bus with access conflicts for read/write at high speed in an arbitrary timing of the CPU without increasing load of the CPU. SOLUTION: An address decoder part 102 notifies an instruction of stopping DMA transfer so as not to give an access right to the plurality of DMAC parts during DMA transfer when detecting the start of an access from the CPU 101 to a memory part 108. After receiving a signal indicating that the DMA transfer is stopped from an arbiter part 103, an access from the CPU101 to the memory part 108 is started. Other than during the DMA transfer, the instruction of stopping the DMA transfer is notified to the arbiter part 103 so as not to give an access right to the plurality of DMAC parts, and then an access from the CPU 101 to the memory part 108 is started. COPYRIGHT: (C)2008,JPO&INPIT
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