NON-CONFORMAL STRESS LINER FOR ENHANCED MOSFET PERFORMANCE

摘要

A non-conformal stress liner for enhanced MOSFET performance is provided to enhance stress and carrier mobility by reducing or removing an offset spacer and including a non-conformal stress liner. A semiconductor structure includes a semiconductor substrate(12) having at least one FET(Field Effect Transistor) on the semiconductor substrate, at least one reduced offset spacer, and a non-conformal stress liner(30). The non-conformal stress liner is formed to surround a part of the semiconductor substrate and the FET. The non-conformal stress liner is composed of a compressive stress liner. The non-conformal stress liner is a tensile stress liner. In the semiconductor structure, at least one FET is a pFET and an nFET and the non-conformal stress liner surrounding the pFET is a compressive stress liner and the non-conformal stress liner surrounding the pFET is a tensile stress liner.