| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce a jitter component in a clock signal output from a PLL circuit with a simplified circuit construction. <P>SOLUTION: The semiconductor integrated circuit device 1 comprises: an input terminal 10 for inputting a reference frequency signal SG; a bandpass filter circuit 20 connected with the input terminal 10 for passing the reference frequency signal SG; and a PLL circuit 30 for inputting an output signal of the band pass filter circuit 20 as a reference signal via a CMOS inverter circuit INV2. To the input terminal 10 the reference frequency signal SG is supplied which is generated by a quartz oscillator etc. packaged outside the semiconductor integrated circuit device 1. The band-pass filter circuit 20 limits bandpass components other than the frequency of the reference frequency signal SG for a signal supplied to the input terminal 10 and supplies the reference signal to the PLL circuit 30. The PLL circuit 30 operates taking the reference frequency signal SG as a reference signal. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
