| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the processing load of a DSP without increasing memory capacity. <P>SOLUTION: The processor comprises the DSP 32 for decoding voice data; a buffer memory 36 that is a ring buffer successively storing and holding voice data; a data read control part 46 which reads the voice data stored in the buffer memory 36; an FIFO 40 for DAC or an FIFO 44 for DIT which stores and holds the voice data input from the data read control part 46; and a DAC 38 or DIT 42 which outputs an interruption signal to the data read control part 46 when the voice data held in the FIFO is a predetermined quantity or less. The data read control part 46 reads the voice data held in the buffer memory 36 when the interruption signal is input, and the value of a write pointer is equal to the value of a read pointer. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
