发明名称 ADAPTIVE GATE VOLTAGE REGULATION
摘要 A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
申请公布号 WO2008055183(A2) 申请公布日期 2008.05.08
申请号 WO2007US83062 申请日期 2007.10.30
申请人 ATMEL CORPORATION;SIVERO, STEFANO;SURICO, STEFANO;CASER, FABIO TASSAN;CHINOSI, MAURO 发明人 SIVERO, STEFANO;SURICO, STEFANO;CASER, FABIO TASSAN;CHINOSI, MAURO
分类号 G11C16/10 主分类号 G11C16/10
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