| 摘要 |
<p>A method for manufacturing a gate electrode of a semiconductor memory device is provided to enhance reliability and productivity by suppressing generation of a fitting effect on a semiconductor substrate. A silicon oxide layer, a first polysilicon layer, an ONO layer including upper oxide-nitride-lower oxide layers, and a second polysilicon layer are deposited on a semiconductor substrate(S200). A control gate is formed by etching the second polysilicon layer. A gate interlayer dielectric layer is formed by performing a wet-etch process for the upper oxide layer, a dry-etch process for the nitride layer, and the wet-etch process for the lower oxide layer(S204,S206,S208). A floating gate is formed by patterning the first polysilicon layer(S210). A tunnel oxide layer is formed by etching the silicon oxide layer(S212).</p> |
