| 摘要 |
A solid state imaging system has at least one CMOS imager (190) with firs t and second series of pixels (191, 192, 193) in which the pixels of one ser ies are offset, i.e., staggered, in respect to the pixels of the other serie s. Multiple imagers can be arrayed end to end, with jumper wires (48) connec ting the pixel output conductors or each so that the pixels feed into a comm on output amplifier (160, 161 ) for each series, to minimize chip to chip of fset voltages. The pixels may be diagonally offset from one another, and a c olor imager can be constructed in which color ribbon filters are arranged di agonally across the imaging area. This arrangement minimizes color cross tal k. An array of microlenses (200, 210, 210', 211) is situated with each micro lens covering a plurality of the pixels. The pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the i mager(s).
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