发明名称 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To effectively prevent erroneous reading or the like while reducing the size of a row decoder. <P>SOLUTION: A local row decoder 3 is configured such that a selection switch 123 including a p-channel MOS transistor 121 and an n-channel MOS transistor 122 is connected to each word line WL. The drain of the p-channel MOS transistor 121 and the drain of the n-channel MOS transistor 122 are both connected to the word line WL. The gates of the p-channel MOS transistor 121 and the n-channel MOS transistor 122 connected to the common word line WL are connected in common to a single global word line GWL. The source of the n-channel MOS transistor 122 is connected to a first block decode line BD1. On the other hand, the source of the p-channel MOS transistor 121 is connected to a second block decode line BD21 or BD22. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008108382(A) 申请公布日期 2008.05.08
申请号 JP20060291557 申请日期 2006.10.26
申请人 TOSHIBA CORP 发明人 UMEZAWA AKIRA
分类号 G11C16/06;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 G11C16/06
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