发明名称 HIGHLY-SCALABLE HARDWARE-BASED TRAFFIC MANAGEMENT WITHIN A NETWORK PROCESSOR INTEGRATED CIRCUIT
摘要 A technique for managing traffic within a network processor integrated circuit (IC) involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps.
申请公布号 US2008107020(A1) 申请公布日期 2008.05.08
申请号 US20070935298 申请日期 2007.11.05
申请人 TRINH MAN;CHEN STEVE;CHANG MARTIN;CHEN RAY 发明人 TRINH MAN;CHEN STEVE;CHANG MARTIN;CHEN RAY
分类号 G08C15/00;H04J3/14;H04L12/56 主分类号 G08C15/00
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