| 摘要 |
An application specific integrated circuit (ASIC) uses a dedicated interface between its core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core. The ASIC has a controller configured as the interface and a plurality of receivers connected to the SBus, distributed about the chip. The controller interfaces with the core asynchronously. The controller may have a test interface that operates asynchronously to the core interface. The controller may have a programmable divider to configure the SBus clock. The controller may have a state machine that issues consecutive SBus commands at set intervals. Each of the receivers may have a plurality of clocks, each clock having a distinct period from the other clocks. Also, disclosed is a method of providing the SBus capabilities to the core by coupling the core to the SBus controller via a multiple conductor interface. In addition, a method of testing the ASIC is disclosed. The method of testing comprises receiving a set of commands to exercise a function on the ASIC and directing the transfer of select commands. |
