| 摘要 |
A semiconductor device testing apparatus is provided to control test pin groups individually by allocating the test pin group to a test controller on-line. A semiconductor device testing apparatus includes test controllers(10-1 to 10-N), variable clock generators(24-1 to 24-N), test pin groups(12-1 to 12-N), a first N x N switch matrix(16), and a second N x N switch matrix(18). The variable clock generators output variable clock signals which have a constant phase relation with respect to a control signal from the test controller. The test pin groups perform a test on a DUT(Device Under Test) based on a control signal synchronized with the variable clock signal. The first N x N switch matrix supplies the control signal from the one test controller, namely 10-i, to a test pin group, namely 12-j, which is allocated to the test controller. The second N x N switch matrix supplies the variable clock signal from the variable clock generator, namely 24-i, corresponding to the test controller to a test pin group, namely 12-j.
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