发明名称 |
Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width |
摘要 |
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.
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申请公布号 |
US7370132(B1) |
申请公布日期 |
2008.05.06 |
申请号 |
US20050281718 |
申请日期 |
2005.11.16 |
申请人 |
NVIDIA CORPORATION |
发明人 |
HUANG WEI JE;BISSON LUC R.;RUBINSTEIN OREN;DIAMOND MICHAEL B.;SIMMS WILLIAM B. |
分类号 |
G06F13/40 |
主分类号 |
G06F13/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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