发明名称 NESTED VOLTAGE ISLAND ARCHITECTURE
摘要 An integrated circuit. The integrated circuit includes a parent terrain; and a hierarchical order of nested voltage islands within the parent terrain, each higher-order voltage island nested within a lower-order voltage island, each nested voltage island having the same hierarchical structure.
申请公布号 KR100827056(B1) 申请公布日期 2008.05.02
申请号 KR20067000054 申请日期 2006.01.02
申请人 发明人
分类号 H01L27/02;G06F9/45;H01L;H01L23/528 主分类号 H01L27/02
代理机构 代理人
主权项
地址