发明名称 SEMICONDUCTOR PACKAGE AND STACKED LAYER TYPE SEMICONDUCTOR PACKAGE
摘要 A semiconductor package and a stack type semiconductor package are provided to decrease a thickness of the semiconductor package by mounting a semiconductor chip on a concave portion of a silicon substrate. A semiconductor package includes a semiconductor chip(301), a substrate(101), and a line structure(200). A concave portion is formed on the substrate. The semiconductor chip is mounted in the concave portion. The line structure is configured on or under the semiconductor chip to be connected with the outside. The semiconductor chip is mounted on the concave portion in a face down shape. The line structure includes a via plug(201), which penetrates a bottom portion of the concave portion of the substrate. The line structure includes a pattern line(202), which has a portion formed on a sidewall of the concave portion.
申请公布号 KR20080038035(A) 申请公布日期 2008.05.02
申请号 KR20070107806 申请日期 2007.10.25
申请人 SHINKO ELECTRIC INDUSTRIES CO., LTD. 发明人 YAMANO TAKAHARU;KOBAYASHI TSUYOSHI
分类号 H01L23/12 主分类号 H01L23/12
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