发明名称 INVERTER CIRCUIT, AND DELAY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an inverter circuit that reduces a circuit scale, prevents a through-current from flowing, and reduces power consumption when applied to a delay circuit or the like. SOLUTION: The inverter circuit is provided with a MOS transistor P11 turned on/off by an input signal IN1, an N-type MOS transistor N11 turned on/off by an input signal IN2, and two MOS transistors P12, N12 connected in series while being connected with a gate and a drain. The MOS transistor P11, the MOS transistors P12, N12, and the MOS transistor N11 are serially connected between a first power supply VDD and a second power supply VSS. An output signal OUT1 is extracted from a common coupling joint between the MOS transistors P11, P12. An output signal OUT2 is extracted from a common coupling joint between the MOS transistors N11, N12. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008104053(A) 申请公布日期 2008.05.01
申请号 JP20060286030 申请日期 2006.10.20
申请人 SEIKO EPSON CORP 发明人 KUBOTA SATORU
分类号 H03K19/20;H03F3/16;H03K5/13;H03K17/16;H03K17/687;H03K19/0948 主分类号 H03K19/20
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