| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a system-on-chip including a retention input/output device achieving low power even if the system-on-chip is in a sleep mode. <P>SOLUTION: This system-on-chip has: a control part generating a first input/output control signal determining an input/output state in a normal N-mode, a second input/output control signal determining an input/output state in a sleep S-mode, a normal value, and a sleep value; first-fourth registers storing the first and second input/output control signals, the normal value, and the sleep value; a first selector selecting one of the first and second input/output control signals; an internal logic circuit responding to the normal value and generating a transmission signal to the outside; a second selector selecting one of fourth register output and internal logic circuit output; a power control part controlling the first and second selectors; and the retention input/output device storing output of the first and second selectors when switched to the S-mode from the N-mode. When the N-mode turns to the S mode, an input/output state of the retention input/output device is held by the output of the first selector. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
