| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that access performance may be degraded because a bank not actually accessed becomes busy for a fixed period in a system using a memory having a plurality of banks. SOLUTION: A memory access controller is provided with an access request bank analysis part 110 for generating access request bank information S02 indicating a memory band to be accessed according to a memory access request signal S01, a bank use state information storage part 125 for storing the access request bank information S02 for a fixed cycle period as bank use state information S03, and an access permission signal generation part 130 for generating an access permission signal S04 for controlling whether a subsequent memory bank access is to be received or not by the access request bank information S02 and the bank use state information S03. The bank use state information S03 concerned with the memory bank whose access is permitted is updated according to access information S06 such as transfer direction information, access unit information, and memory initialization information. COPYRIGHT: (C)2008,JPO&INPIT
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