发明名称
摘要 A data processing circuit has a programmable processor (12a, b) with an instruction set that comprises an new type of instruction. This instruction has a first operand that refers to a string of bits, and a second operand that refers to a position in that string of bits. The programmable processor (12a, b) is arranged to execute this type of instruction by returning, as a result, a code that is indicative of a count of a number of bits that occurs from said position in the string of bits until the string of bits from said position deviates from a predetermined bit pattern. The instruction is particularly useful for use in programs that perform variable length decoding and/or decoding.
申请公布号 JP2008514095(A) 申请公布日期 2008.05.01
申请号 JP20070531935 申请日期 2005.09.15
申请人 发明人
分类号 H03M7/40 主分类号 H03M7/40
代理机构 代理人
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