发明名称 DYNAMICALLY SCALABLE CACHE ARCHITECTURE
摘要 A technique for managing power consumption of a cache memory system dynamically adjusts the size of the cache memory system according to an energy level of an energy storage device. In at least one embodiment of the invention, an apparatus includes a dynamically scalable cache memory circuit including at least one cache memory circuit having an effective cache size selectable from a plurality of cache sizes. The apparatus includes a control circuit responsive to an energy level indicator of at least an approximate energy level of an energy storage device configured to provide energy to the dynamically scalable cache memory circuit. The control circuit is configured to select the effective cache size based at least in part on the energy level indicator.
申请公布号 US2008104324(A1) 申请公布日期 2008.05.01
申请号 US20060553560 申请日期 2006.10.27
申请人 ADVANCED MICRO DEVICES, INC. 发明人 RAGHUVANSHI PREETHAM
分类号 G06F12/00 主分类号 G06F12/00
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