<p>An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.</p>
申请公布号
EP1916794(A2)
申请公布日期
2008.04.30
申请号
EP20070119334
申请日期
2007.10.25
申请人
FUJITSU TEN LIMITED;FUJITSU LIMITED;RENESAS TECHNOLOGY CORP.