发明名称 |
Verification and generation of timing exceptions |
摘要 |
<p>The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing one or more potential malfunctions of the logic circuit related to the one or more exceptions into the representation of the logic circuit to produce a modified representation of the logic circuit; a fourth step of determining whether functional behaviour of the modified representation of the logic circuit differs from functional behaviour of the first representation of the logic circuit; and a fifth step of reporting a result relating to the difference in the functional behaviour of the modified representation of the logic circuit from the functional behaviour of the initial representation of the logic circuit.</p> |
申请公布号 |
EP1916534(A1) |
申请公布日期 |
2008.04.30 |
申请号 |
EP20060022162 |
申请日期 |
2006.10.23 |
申请人 |
ONESPIN SOLUTIONS GMBH |
发明人 |
MUELLER-BRAHMS, MARTIN DR. RER. |
分类号 |
G01R31/3181;G06F17/50 |
主分类号 |
G01R31/3181 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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