| 摘要 |
The invention relates to a cache memory with a four (4) stage pipeline that can be arranged between a processor and a low-speed memory. The processor requests data from the cache memory using an input address (which splits into a tag address (which is loaded into a latch circuit) and an index address). The cache memory comprises two main data stores: a data memory to store a subset of data corresponding to the low-speed memory and a tag memory to hold tag address corresponding to the data stored in the data memory. It also comprises a hit decision unit which is used to decide whether there has been a cache hit or a cache miss. This is done by comparing tag addresses acquired by searching the tag memory using the processor supplied index address with the tag address supplied in the input address. Further, it has a bypass circuit which can be used to supply the tag address held in the latch circuit direct to the hit decision unit. On a cache miss, a controller is configured to update the tag memory using the tag address in the input address, load the correct data into the data memory from the slow-memory and modify the behaviour of the bypass circuit. |
