发明名称
摘要 <p>PROBLEM TO BE SOLVED: To provide a memory control device which sets order of priority to a memory access and efficiently mediates a memory access demand so that they do not fail. SOLUTION: In a memory control device which mediates a memory access for allowing an access demand to a buffer memory from plural circuit blocks including error correction blocks for requiring N times of accesses to the buffer memory according to predetermined order of priority during a specified frame term T, the device has a comparison means 24 having a numerical value M predetermined as a comparison reference value and an up down count means 25 which counts up every cycle T/(N+M) and, if the memory access is allowed, counts down. The count value of the up down count means 25 and the reference value M are compared by the comparison means 24 and the order of priority of the error correction block is changed in accordance with the comparison output.</p>
申请公布号 JP4081843(B2) 申请公布日期 2008.04.30
申请号 JP19980077061 申请日期 1998.03.25
申请人 发明人
分类号 G06F12/16;G06F12/00;G11C16/02 主分类号 G06F12/16
代理机构 代理人
主权项
地址