| 摘要 |
A cryptographic logic circuit, comprising: ```a first logic unit configured to execute at least one logic operation for a plurality of data pairs, the data pairs including random data and random masking data; and ```a second logic unit configured to execute a logic operation for the results of the first logic unit; ```wherein the first logic unit 101 includes: ```a first AND gate 102 configured to execute a first logic AND operation with first and second random masking data X', Y': ```a second AND gate 103 configured to execute a second logic AND operation with the first random masking data X' and second random data S; ```a third AND gate 104 configured to execute a logic third AND operation with first random data R and the second random masking data Y'; and ```a fourth AND gate 105 configured to execute a logic fourth AND operation with the first and second random data R, S; ```and wherein the second logic unit 107 includes: ```a first XOR gate 108 configured to execute a first logic XOR operation with the output of the first AND gate, the second AND gate, and the second random masking data; and ```a second XOR gate 109 configured to execute a second logic XOR operation with the output of the third AND gate, the fourth AND gate, and the second random masking data. The cryptographic logic circuit may be a cryptographic AND logic circuit comprising a random masking scheme and having security against a power analysis attack. |
