发明名称 |
STRUCTURE AND METHOD FOR FORMING INTER-POLY DIELECTRIC IN A SHIELDED GATE FIELD EFFECT TRANSISTOR |
摘要 |
<p>A shielded gate trench FET is formed as follows. A trench is formed in a silicon region of a first conductivity type, the trench including a shield electrode insulated from the silicon region by a shield dielectric. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.</p> |
申请公布号 |
KR20080035686(A) |
申请公布日期 |
2008.04.23 |
申请号 |
KR20087005785 |
申请日期 |
2006.08.04 |
申请人 |
FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
HERRICK ROBERT;PROBST DEAN E.;SESSION FRED |
分类号 |
H01L21/336;H01L29/78 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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