发明名称 METHOD AND APPARATUS FOR DISABLING A CLOCK SIGNAL WITHIN A MULTITHREADED PROCESSOR
摘要 <p>A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.</p>
申请公布号 EP1236107(B1) 申请公布日期 2008.04.23
申请号 EP20000970828 申请日期 2000.10.11
申请人 INTEL CORPORATION 发明人 RODGERS, DION;TOLL, BRET;WOOD, AMIEE
分类号 G06F9/46;G06F15/00;G06F9/38 主分类号 G06F9/46
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