发明名称 |
Integrated circuit metrology |
摘要 |
Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device. Problematic areas, within a chip or die and within a wafer, are identified that result from process variation. The variation is identified and characterized, and the location of each site is stored. The sites may be manually entered into a metrology tool or the method will automatically generate a measurement plan. Process variation and electrical impact are used to direct the measurement of within-die and wafer-level integrated circuit locations.
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申请公布号 |
US7363099(B2) |
申请公布日期 |
2008.04.22 |
申请号 |
US20020200660 |
申请日期 |
2002.07.22 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
SMITH TABER H.;WHITE DAVID |
分类号 |
G06F19/00;G01Q30/02;G01Q60/00;G01Q80/00;G01Q90/00;G06F9/45;G06F17/50;H01L21/3105;H01L21/321 |
主分类号 |
G06F19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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