| 摘要 |
A circuit for controlling pulse width of a column selection signal is provided to control delay period determining pulse width of the column selection signal according to internal operation of a semiconductor device. A delay part(2) generates a reset signal with a controlled enable period according to a predetermined delay period. A latch part(1) controls pulse width of a column selection signal in response to the reset signal. A pulse width control part(3) generates a first and a second control signal to control the delay period of the delay part. A signal transfer part(4) transfers the first and the second control signal to the delay part selectively in response to an internal read command signal enabled according to a read command, an internal write command signal enabled in response to a write command and fuse cutting.
|
