Phase and frequency comparator used in digital phase-locked loop (PLL), has differential unit that has output for transmitting phase error word with predetermined word width as function of difference between counter word and integrator word

摘要

The phase and frequency comparator (PFD) has a counter module (MC) that has an output (41) for transmitting a counter word (CW) having predetermined word width based on an oscillator signal (OSC). An integrator module (MI) has an output (42) for transmitting an integrator word (IW) with a predetermined word width as an integration function of a channel word (CH). A differential unit (S1) has an output (32a) for transmitting a phase error word (PW) with predetermined word width as a function of the difference between the counter word and integrator word. Independent claims are also included for the following: (1) Phase and frequency detection; (2) Oscillator signal generation process; and (3) Use of the phase and frequency detector.