发明名称 |
METHOD FOR CALCULATING POWER CONSUMPTION OF SEMICONDUCTOR INTEGRATED CIRCUIT AND APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
<p>In preprocessing (S11), based on logic determining circuit information, circuit elements of a logic determining circuit prior to layout designing are grouped into a plurality of circuit groups in accordance with an input clock. In operation rate calculating processing (S12), based on operation result information obtained by logic verification relating to the logic determining circuit, an average operation rate is calculated for each circuit group. In power consumption calculation processing (S13), based on the calculated average operation rate and layout designed circuit information after layout designing, power consumption in the circuit after layout designing is calculated. Thus, power consumption analysis for the circuit after the layout designing is easily and highly accurately performed by using the operation result information obtained from the logic verification which can be executed at a high speed.</p> |
申请公布号 |
WO2008041280(A1) |
申请公布日期 |
2008.04.10 |
申请号 |
WO2006JP319473 |
申请日期 |
2006.09.29 |
申请人 |
FUJITSU LIMITED;NIITSUMA, JUNICHI;FUJITA, RYUJI;TAMAKI, KAZUHIDE;SASAKI, TAKAYUKI |
发明人 |
NIITSUMA, JUNICHI;FUJITA, RYUJI;TAMAKI, KAZUHIDE;SASAKI, TAKAYUKI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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