发明名称 |
Hierarchical cache coherence directory structure |
摘要 |
A method for maintaining cache coherence comprises coordinating operations among a plurality of processors distributed among a plurality of nodes coupled by an interconnect fabric and managing cache coherence in a plurality of memory directories respectively associated with the processor plurality in combination with a node controller directory cache associated with a node controller coupled between the processor plurality and the interconnect fabric. The method further comprises maintaining memory coherence directory information comprising identifying processors within a node in a first portion of bits of a memory directory entry coupled to an associated processor in the node and identifying subsets of processors external to the node in the system in a second portion of bits.
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申请公布号 |
US2008086601(A1) |
申请公布日期 |
2008.04.10 |
申请号 |
US20060544690 |
申请日期 |
2006.10.06 |
申请人 |
GAITHER BLAINE D;KNAPP VERNA |
发明人 |
GAITHER BLAINE D.;KNAPP VERNA |
分类号 |
G06F13/28 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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