发明名称 |
Processor, Data Processing System and Method Supporting a Shared Global Coherency State |
摘要 |
A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. According to a method of data processing, a cache line is buffered in a data array of the cache memory and a state field in a cache directory of the cache memory is set to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in said second coherency domain may hold a copy of the cache line.
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申请公布号 |
US2008086602(A1) |
申请公布日期 |
2008.04.10 |
申请号 |
US20060539694 |
申请日期 |
2006.10.09 |
申请人 |
GUTHRIE GUY L;STARKE WILLIAM J;WILLIAMS DEREK E;WILLIAMS PHILLIP G |
发明人 |
GUTHRIE GUY L.;STARKE WILLIAM J.;WILLIAMS DEREK E.;WILLIAMS PHILLIP G. |
分类号 |
G06F13/28 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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