MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF

摘要

A memory (102) includes a bit cell array (120) including a plurality of word lines and address decode circuitry (116) having an output to provide a predecode value. The address decode circuitry (116) includes a first plurality of transistors having a first gate oxide thickness. The memory (102) further includes word line driver circuitry (118) having an input coupled to the output of the address decode circuitry (116) and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.