| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a memory testing device and a memory testing method which can simultaneously execute a plurality of memory tests only by simple address management. <P>SOLUTION: A test processor 1 of the memory testing device is capable of simultaneously writing, reading, or erasing a test signal for each memory block with respect to a plurality of devices (DUT) to be tested. The memory testing device includes a first memory 4 wherein identification values specifying bad blocks of respective DUTs are recorded and a second memory 5 wherein AND data resulting from AND operations by referring to the identification values for each memory block of respective DUTs is recorded, and a memory test that only DUTs having no bad blocks are successively selected by a DUT number identification part 3 to write, read, and erase the test signal to/from the DUTs, can be performed in a memory block which is determined to include bad blocks by a block determination part 2. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
