| 摘要 |
In one embodiment of the invention, an address decoder for decoding a word-line address to energize a word line in a block of computer memory. Instead of relying on a distinct enable signal, a clock signal provides a reset function and an enable function to the address decoder. In one implementation, the address decoder includes negative-level-sense latches and 3-input AND gates to generate decoded address bits. Using the clock signal as one of the inputs to the AND gates ensures that all of the decoded address bits are 0 when the clock signal is low and that exactly one decoded address bit is 1 when the clock signal is high. In this way, the address decoder ensures that two or more word lines are not energized at the same time.
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