发明名称 |
APPARATUS FOR ELIMINATING LEAKAGE CURRENT OF A LOW Vt DEVICE IN A COLUMN LATCH |
摘要 |
An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.
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申请公布号 |
US2008084767(A1) |
申请公布日期 |
2008.04.10 |
申请号 |
US20060539564 |
申请日期 |
2006.10.06 |
申请人 |
ATMEL CORPORATION |
发明人 |
CHAN JOHNNY;TSAI JEFFREY MING-HUNG;WONG TIN-WAI |
分类号 |
G11C7/10;G11C11/00;G11C11/34;G11C16/06 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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地址 |
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