| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a fast Fourier transform circuit allowing reduction of an arithmetic error. <P>SOLUTION: To each of a 2<SP>n</SP>number of pieces of input data of a prescribed number of bits, data of the same number of bits as the prescribed number of bits, in a range predetermined as an effective range by butterfly computation are extracted from each computation result data calculated by performing the butterfly computation according to each stage by an FFT (Fast Fourier Transform) computation part 22 in each stage by a bit extraction part 24, each the extracted data of the prescribed number of bits are set as the input data when performing the butterfly computation in the next stage by the FFT computation part 22. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
