| 摘要 |
PROBLEM TO BE SOLVED: To easily reserve the operation margin during write operation in a DRAM and the like for which a high-frequency operation is required. SOLUTION: For example, a WENB generation circuit 18-1 provided within a read-write control circuit generates a pulse PULSE having an activation period regulated by an RC delay section 18a comprising a resistance element R and a capacitor element C synchronized with an internal clock CLKIN. The generated pulse PULSE is then inverted by an inverter circuit INVd of an output section and is outputted as a write activation signal WENB to inactivate the pulse PULSE in a write operation period (activation period) of SA. COPYRIGHT: (C)2008,JPO&INPIT
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