Methods for fabricating a stressed MOS device

摘要

Methods are provided for fabricating a stressed MOS device [30]. The method comprises the steps of forming a plurality of parallel MOS transistors in and on a semiconductor substrate [36]. The parallel MOS transistors having a common source [92] region, a common drain [94] region, and a common gate electrode [66]. A first trench [82] is etched into the substrate in the common source [92] region and a second trench [84] is etched into the substrate in the common drain [94] region. A stress inducing semiconductor material [90] that has a crystal lattice mismatched with the semiconductor substrate is selectively grown in the first [82] and second [84] trenches. The growth of the stress inducing material [90] creates both compressive longitudinal and tensile transverse stresses in the MOS device channel [50] that enhance the drive current of P-channel MOS transistors. The decrease in drive current of N-channel MOS transistors caused by the compressive stress component is offset by the tensile stress component.