发明名称
摘要 A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25� C. is not more than that of the second insulating layers, each of the third wiring layers and each of the third insulating layers being alternately laminated.
申请公布号 JP4072523(B2) 申请公布日期 2008.04.09
申请号 JP20040208375 申请日期 2004.07.15
申请人 发明人
分类号 H01L21/768;H01L21/3205;H01L23/52;H01L23/522 主分类号 H01L21/768
代理机构 代理人
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