| 摘要 |
A processor 2 uses register renaming to map logical registers in instructions to physical registers in the processor. For instructions which use a large number of registers, the processor divides the renaming tasks into an initial set and a remaining set. The initial renaming tasks are performed first and the results passed via a main channel 32 to the execution units 18, 20, 22, 24. The remaining renaming tasks are then performed with the results being passed via a background channel 34 to the execution units. At the same time, as the remaining mappings are being sent on the background channel, mappings for new instructions are sent along the main channel. The remaining mappings may be generated and output in sequence. |
