发明名称 |
Performing read and write operations in the same cycle for an SRAM device |
摘要 |
A decoding signal circuit is configured to generate a dual operation decoding signal that enables a read operation and a write operation to be performed in one clock cycle. The decoding signal circuit is configured such that a read decoding signal and a write decoding signal are generated and multiplexed together to form the dual operation decoding signal. The memory device receives a read address and a write address consecutively in one cycle to generate the dual operation decoding signal. A single operation, such as a read only operation or a write only operation, can be performed as well as the dual operation of performing the read operation and the write operation in the same cycle.
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申请公布号 |
US7355907(B2) |
申请公布日期 |
2008.04.08 |
申请号 |
US20060404191 |
申请日期 |
2006.04.14 |
申请人 |
SONY CORPORATION;SONY ELECTRONICS |
发明人 |
CHEN HSIN-LEY SUZANNE;TSENG CHIH-CHIANG;HUANG MU-HSIANG |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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