| 摘要 |
A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and provides an FD output signal. A summer is coupled to the PD and FD for summing the PD and FD output signals, and for providing a summer output signal. The CDR further comprises a voltage-controlled oscillator (VCO) for receiving a direct current signal and providing a recovered clock signal. A polyphase filter is coupled to each of the VCO, PD, and QP detector. A re-timer is coupled to the polyphase filter and provides a re-timed data signal, wherein the CDR circuit is on-chip and the polyphase filter converts clock signals into phase reference signals.
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