| 摘要 |
A video decoder ( 52, 152 ) including a digital-control oscillator (DCO) ( 60, 160 ) is disclosed. The DCO ( 60, 160 ) includes a first flying-adder frequency synthesis circuit ( 74 S) that measures an input signal frequency, such as the horizontal sync frequency of an input video signal. A frequency control word (FREQ) is generated in response to this input signal frequency, and is applied to a second flying-adder frequency synthesis circuit ( 74 ), which in turn selects the appropriate phases for leading and trailing edges of the output clock signal (PIX_CLK). Phase tuning of the output clock signal (PIX_CLK) can be effected by using an alternate flying-adder frequency synthesis circuit ( 74 ') architecture, in combination with a phase signal (PH) generated by a digital controller ( 61 ). Multiple phase-tuned sample clocks (PIX_CLK_A, PIX_CLK_B, PIX_CLK_C) can be similarly generated from multiple flying-adder frequency synthesis circuits ( 174 A, 174 B, 174 C), each controlled by the frequency control word (FREQ) and a corresponding phase signal (PHA, PHB, PHC). Video mode control logic ( 65, 165 ) can also be implemented by way of a similar DCO architecture. The DCO ( 60 ) may be used to generate a clock signal at a large frequency multiple relative to the input signal, outside of the video decoder context.
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