发明名称 Dynamic bias circuit for use with a stacked device arrangement
摘要 A regulator circuit includes a first transistor coupled to a supply voltage and a second transistor coupled between the first transistor and an output node. The regulator circuit also includes a dynamic bias circuit that may selectively provide a bias voltage to a gate of the second transistor. During a first mode such as a low power mode, for example, the bias circuit may provide the bias voltage at a fixed percentage of the supply voltage as the supply voltage varies. In addition, during a second mode such as a high power mode, for example, the bias circuit may provide the bias voltage at a fixed offset from the supply voltage as the supply voltage varies.
申请公布号 US7355375(B2) 申请公布日期 2008.04.08
申请号 US20050241285 申请日期 2005.09.30
申请人 NXP B.V. 发明人 XI XIAOYU
分类号 G05F1/40;G05F1/56 主分类号 G05F1/40
代理机构 代理人
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