发明名称 Timing exact design conversions from FPGA to ASIC
摘要 Timing exact design conversions from an original field programmable device to an application specific device is disclosed. In a first aspect, a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC) comprises a user configurable element in the FPGA replaced by a mask configurable element in the ASIC. In a second aspect, an FPGA design conversion to an ASIC comprises converting a user configurable memory bit pattern generated by a software tool to program the programmable content of the FPGA to a hard-wired metal pattern for the ASIC.
申请公布号 US7356799(B2) 申请公布日期 2008.04.08
申请号 US20060384116 申请日期 2006.03.20
申请人 VICICIV TECHNOLOGY, INC. 发明人 MADURAWE RAMINDA UDAYA
分类号 G06F17/50;H03K19/177 主分类号 G06F17/50
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