| 摘要 |
A method for manufacturing a semiconductor device is provided to prevent a misalignment between a bit line and a metal contact plug by forming grooves and spacers on both sides of the grooves. A cell region and a peripheral region are defined on a semiconductor substrate(10). A bit line comprised of a barrier layer(20), a conductive layer(30) for a wire, and a nitride-based hard mask layer is formed on the semiconductor substrate. A first spacer(60) is formed on both sidewalls of the bit line. A first planarized interlayer dielectric(70) is formed on the semiconductor substrate. A capping layer(80) is formed on the first interlayer dielectric including the bit line of the cell region. The bit line hard mask layer including the first spacer formed on both sidewalls of the bit line hard mask layer of the peripheral region is selectively removed by using the capping layer as an etching mask to form a groove exposing the bit line conductive layer. A second spacer(90) is formed at both sides of the groove. A second interlayer dielectric(100) is formed on the whole surface of the substrate to gap-fill the groove on which the second spacer is formed. The second interlayer dielectric of the cell region is etched to form a contact hole(C) exposing the substrate part. A contact plug(110) for a storage node is formed in the contact hole. A mold dielectric(120) is formed on the whole subface of the substrate including the contact plug for a storage node. A hole(130) for defining a storage node(140) is formed on the mold dielectric. A capacitor is formed on the mold dielectric. A third interlayer dielectric(180) is formed on the whole surface of the substrate including the capacitor. The third interlayer dielectric is etched to form a contact hole exposing the bit line conductive layer of the peripheral region. A metal contact plug(190) is formed in the contact hole.
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