MODELING FOR SEMICONDUCTOR FABRICATION PROCESS EFFECTS

摘要

In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined, such as a gate or interconnect. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates variation factors that may occur in the photolithographic process. One or more adjusted widths and adjusted lengths of the object are then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor or interconnect using the adjusted width and adjusted length.